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ltc2493 1 2493fd typical a pplica t ion fea t ures a pplica t ions descrip t ion 24-bit 2-/4-channel ds adc with easy drive input current cancellation and i 2 c interface the ltc ? 2493 is a 4-channel (2-channel differential), 24-bit, no latency ? tm adc with easy drive technology and a 2-wire, i 2 c interface. the patented sampling scheme elimi - nates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and rail-to-rail input signals to be directly digi- tized while maintaining exceptional dc accuracy. the ltc2493 includes a high accuracy temperature sensor and an integrated oscillator. this device can be configured to measure an external signal (from combi- nations of 4 analog input channels operating in single- ended or differential modes) or its internal temperature sensor. the integrated temperature sensor offers 1/30th c resolution and 2c absolute accuracy. the ltc2493 allows a wide common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid. access to the multiplexer output en- ables optional external amplifiers to be shared between all analog inputs and auto-calibration continuously removes their associated offset and drift. data acquisition system with temperature compensation n up to 2 differential or 4 single-ended inputs n easy drive tm technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 2-wire i 2 c interface with 9 addresses plus one global address for synchronization n 600nv rms noise n integrated high accuracy temperature sensor n gnd to v cc input/reference common mode range n programmable 50hz, 60hz or simultaneous 50hz/60hz rejection mode n 2ppm inl, no missing codes n 1ppm offset and 15ppm full-scale error n 2 speed/reduced power mode (15hz using internal oscillator and 80a at 7.5hz output) n no latency: digital filter settles in a single cycle, even after a new channel is selected n single supply 2.7v to 5.5v operation (0.8mw) n internal oscillator n tiny 4mm 3mm dfn package n direct sensor digitizer n direct temperature measurement n instrumentation n industrial process control temperature sensor sda scl f o ref + v cc 2.7v to 5.5v 0.1f com ref ? 24-bit ? adc with easy-drive 4-channel mux in + in ? 2493 vta01a 2-wire i 2 c interface 1.7k ca1 ca0 9-pin selectable addresses ch0 ch1 ch3 ch2 10f osc integrated high performance temperature sensor temperature (c) ?55 ?30 ?5 absolute error (c) 5 4 3 2 1 ?4 ?3 ?2 ?1 0 12095704520 2493 ta02 ?5 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no latency ds and easy drive are trademarks of linear t echnology corporation. all other trademarks are the property of their respective owners.
ltc2493 2 2493fd a bsolu t e maxi m u m r a t ings (notes 1, 2) or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2493cde#pbf ltc2493cde#trpbf 2493 14-lead (4mm 3mm) plastic dfn 0c to 70c ltc2493ide#pbf ltc2493ide#trpbf 2493 14-lead (4mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ supply voltage (v cc ) ................................... C 0 .3v to 6v analog input voltage (ch0 to ch3, com) .................. C 0.3v to (v cc + 0.3v) ref + , ref C .................................. C 0 .3v to (v cc + 0.3v) digital input voltage ..................... C 0.3v to (v cc + 0.3v) digital output voltage .................. C 0.3v to (v cc + 0.3v) operating temperature range ltc2493c ................................................ 0 c to 70c ltc2493i ............................................. C 40c to 85c storage temperature range .................. C 65c to 150c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ref ? ref + v cc ch3 ch2 ch1 ch0 f o ca0 ca1 scl sda gnd com de package 14-lead (4mm 3mm) plastic dfn 15 t jmax = 125c, ja = 37c/w exposed pad (pin 15) is gnd, must be soldered to pcb p in con f igura t ion
ltc2493 3 2493fd e lec t rical c harac t eris t ics ( n or m al s pee d ) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l l 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) l 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in C v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 2.7v < v cc < 5.5v, 2.5v v ref v cc , gnd in + = in C v cc (note 12) 0.6 v rms internal ptat signal t a = 27c (note 13) 27.8 28.0 28.2 mv internal ptat temperature coefficient 93.5 v/c e lec t rical c harac t eris t ics (2x s pee d ) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) l 0.2 2 mv offset error drift 2.5v v ref v cc , gnd in + = in C v cc 100 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c output noise 5v v cc 5.5v, v ref = 5v, gnd in + = in C v cc 0.85 v rms c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) l 140 db input common mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 7) l 140 db input common mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 8) l 140 db input normal mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 7) l 110 120 db input normal mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 8) l 110 120 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in + = in C = gnd 120 db power supply rejection, 50hz 2%, 60hz 2% v ref = 2.5v, in + = in C = gnd (notes 7, 8, 9) 120 db
ltc2493 4 2493fd i 2 c i npu t s a n d digi t al o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) a nalog i npu t an d r e f erence the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage (in + corresponds to the selected positive input channel) gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage (in C corresponds to the selected negative input channel) gnd C 0.3v v cc + 0.3v v v in input differential voltage range (in + C in C ) l Cfs +fs v fs full-scale of the differential input (in + C in C ) l 0.5v ref v lsb least significant bit of the output code l fs/2 24 ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd ref + C 0.1v v v ref reference voltage range (ref + C ref C ) l 0.1 v cc v cs(in + ) in + sampling capacitance 11 pf cs(in C ) in C sampling capacitance 11 pf cs(v ref ) v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd l C10 1 10 na i dc_leak(in C ) in C dc leakage current sleep mode, in C = gnd l C10 1 10 na i dc_leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc l C100 1 100 na i dc_leak(ref C ) ref C dc leakage current sleep mode, ref C = gnd l C100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v v iha low level input voltage for address pins ca0, ca1 and pin f o l 0.05v cc v v ila high level input voltage for address pins ca0, ca1 l 0.95v cc v r inh resistance from ca0, ca1 to v cc to set chip address bit to 1 l 10 k r inl resistance from ca0, ca1 to gnd to set chip address bit to 0 l 10 k r inf resistance from ca0, ca1 to gnd or v cc to set chip address bit to float l 2 m i i digital input current (f o ) l C10 10 a v hys hysteresis of schmitt trigger inputs (note 5) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v t of output fall time v ih(min) to v il(max) bus load c b 10pf to 400pf (note 14) l 20 + 0.1c b 250 ns i in input leakage (sda, scl) 0.1v cc v in 0.9v cc l 1 a c cax external capacitative load on-chip address pins (ca0, ca1) for valid float l 10 pf
ltc2493 5 2493fd p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion current (note 11) temperature measurement (note 11) sleep mode (note 11) l l l 160 200 1 275 300 2 a a a symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) l 10 4000 khz t heo external oscillator high period l 0.125 50 s t leo external oscillator low period l 0.125 50 s t conv_1 conversion time for 1 speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode external oscillator (note 10) l l l 157.2 131 144.1 160.3 133.6 146.9 41036/f eosc (in khz) 163.5 136.3 149.9 ms ms ms ms t conv_2 conversion time for 2 speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode external oscillator (note 10) l l l 78.7 65.6 72.2 80.3 66.9 73.6 20556/f eosc (in khz) 81.9 68.2 75.1 ms ms ms ms digi t al i npu t s a n d digi t al o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda signals (note 14) l 20 + 0.1c b 300 ns t f fall time for sda signals (note 14) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s i 2 c t i m ing charac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3, 15) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: unless otherwise specified: v cc = 2.7v to 5.5v v refcm = v ref /2, f s = 0.5v ref v in = in + C in C , v in(cm) = (in + C in C )/2, where in + and in C are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: 50hz mode (internal oscillator) or f eosc = 256khz 2% (external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses its internal oscillator. note 12: the output noise includes the contribution of the internal calibration operations. note 13: guaranteed by design and test correlation. note 14: c b = capacitance of one bus line in pf (10pf c b 400pf). note 15: all values refer to v ih(min) and v il(max) levels. note 16: refer to applications information section for performance vs data rate graphs.
ltc2493 6 2493fd input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2493 g01 2.5 ?2?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c ?45c 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ? 0.75 ? 0.25 0.25 0.75 2493 g02 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd ? 45c, 25c, 85c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ? 0.75 ? 0.25 0.25 0.75 2493 g03 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd ? 45c, 25c, 85c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?1.5 ? 0.5 0.5 1.5 2493 g04 2.5 ?2?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c ? 45c input voltage (v) ?12 tue (ppm of v ref ) ? 4 4 12 ?8 0 8 ? 0.75 ? 0.25 0.25 0.75 2493 g05 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2493 g06 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c output reading (v) ?3 number of readings (%) 8 10 12 0.6 2493 g07 6 4 ?1.8 ? 0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.60v average = ?0.69v output reading (v) ?3 number of readings (%) 8 10 12 0.6 2493 g08 6 4 ?1.8 ? 0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v t a = 25c rms = 0.59v average = ?0.19v time (hours) 0 ?5 adc reading (v) ?3 ?1 1 10 20 30 40 2493 g09 50 3 5 ? 4 ?2 0 2 4 60 v cc = 5v v ref = 5v v in = 0v v in(cm) = 2.5v t a = 25c rms noise = 0.60v typical p er f or m ance c harac t eris t ics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) noise histogram (7.5sps) long-term adc readings
ltc2493 7 2493fd input differential voltage (v) 0.4 rms noise (v) 0.6 0.8 1.0 0.5 0.7 0.9 ?1.5 ? 0.5 0.5 1.5 2493 g10 2.5 ?2?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c f o = gnd v in(cm) (v) ?1 rms noise (v) 0.8 0.9 1.0 2 4 2493 g11 0.7 0.6 0 1 3 5 6 0.5 0.4 v cc = 5v v ref = 5v v in = 0v t a = 25c f o = gnd temperature (c) ? 45 0.4 rms noise (v) 0.5 0.6 0.7 0.8 1.0 ?30 ?15 15 0 30 45 60 2493 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 rms noise (v) 0.8 0.9 1.0 3.9 4.7 2493 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25c f o = gnd v ref (v) 0 0.4 rms noise (v) 0.5 0.6 0.7 0.8 0.9 1.0 1 2 3 4 2493 g14 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25c f o = gnd v in(cm) (v) ?1 offset error (ppm of v ref ) 0.1 0.2 0.3 2 4 2493 g15 0 ?0.1 0 1 3 5 6 ?0.2 ?0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c f o = gnd temperature (c) ? 45 ? 0.3 offset error (ppm of v ref ) ? 0.2 0 0.1 0.2 ?15 15 30 90 2493 g16 ? 0.1 ? 30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2493 g17 0 ? 0.1 3.1 3.5 4.3 5.1 5.5 ? 0.2 ? 0.3 ref + = 2.5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd v ref (v) 0 ? 0.3 offset error (ppm of v ref ) ? 0.2 ?0.1 0 0.1 0.2 0.3 1 2 3 4 2493 g18 5 v cc = 5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd typical p er f or m ance c harac t eris t ics rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature offset error vs v cc offset error vs v ref
ltc2493 8 2493fd temperature (c) ? 45 ?30 300 frequency (khz) 304 310 ?15 30 45 2493 g19 302 308 306 150 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2493 g20 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 1k 100k 2493 g21 10 100 10k 1m rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 ?140 rejection (db) ?120 ? 80 ? 60 ?40 0 20 100 140 2493 g22 ?100 ?20 80 180 220200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2493 g23 ?80 ?100 30650 30700 30800 ?120 ?140 ?20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c temperature (c) ? 45 100 conversion current (a) 120 160 180 200 ?15 15 30 90 2493 g24 140 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd temperature (c) ? 45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 ?15 15 30 90 2493 g25 0.4 1.6 1.8 1.2 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd output data rate (readings/sec) 0 supply current (a) 500 450 400 350 300 250 200 150 100 80 2493 g26 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in ? = gnd f o = ext osc t a = 25c input voltage (v) ?3 inl (v) ?1 1 3 ?2 0 2 ?1.5 ? 0.5 0.5 1.5 2493 g27 2.5 ?2?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 25c, 85c ? 45c typical p er f or m ance c harac t eris t ics on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v)
ltc2493 9 2493fd input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ? 2 0 2 ? 0.75 ? 0.25 0.25 0.75 2493 g28 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c ? 45c, 25c input voltage (v) ? 3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ? 0.75 ? 0.25 0.25 0.75 2493 g29 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c ?45c, 25c output reading (v) 179 number of readings (%) 8 10 12 186.2 2493 g30 6 4 181.4 183.8 188.6 2 0 16 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.85v average = 0.184mv v ref (v) 0 rms noise (v) 0.6 0.8 1.0 4 2493 g31 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v in(cm) (v) ?1 180 offset error (v) 182 186 188 190 200 194 1 3 4 2493 g32 184 196 198 192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25c temperature (c) ?45 offset error (v) 200 210 220 75 2493 g33 190 180 160 ?15 15 45 ?30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd typical p er f or m ance c harac t eris t ics integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) rms noise vs v ref (2x speed mode) offset error vs v in(cm) (2x speed mode) offset error vs temperature (2x speed mode)
ltc2493 10 2493fd v cc (v) 2 2.5 0 offset error (v) 100 250 3 4 4.5 2493 g34 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v ref (v) 0 offset error (v) 190 200 210 3 5 2493 g35 180 170 160 1 2 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 ?20 ? 40 ? 60 ?80 ?100 ?120 ?140 1k 100k 2493 g36 10 100 10k 1m rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 ?140 rrejection (db) ?120 ?80 ?60 ? 40 0 20 100 140 2493 g37 ?100 ?20 80 180 220200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ? 40 0 30750 2493 g38 ?80 ?100 30650 30700 30800 ?120 ?140 ?20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c typical p er f or m ance c harac t eris t ics offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode)
ltc2493 11 2493fd p in func t ions f o (pin 1): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to gnd, the converter uses its internal oscillator running at 307.2khz. the conversion clock may also be overrid- den by driving the f o pin with an external clock in order to change the output rate and the digital filter rejection null. ca0, ca1 (pins 2, 3): chip address control pins. these pins are configured as a three-state (low, high, floating) address control bits for the devices i 2 c address. scl (pin 4): serial clock pin of the i 2 c interface. the ltc2493 can only act as a slave and the scl pin only accepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. sda (pin 5): bidirectional serial data line of the i 2 c inter - face. in the transmitter mode (read), the conversion result is output through the sda pin, while in the receiver mode (write), the device channel select and configuration bits are input through the sda pin. the pin is high impedance during the data input mode and is an open-drain output (requires an appropriate pull-up device to v cc ) during the data output mode. gnd (pin 6): ground. connect this pin to a common ground plane through a low impedance connection. com (pin 7): the common negative input (in C ) for all single-ended multiplexer configurations. the voltage on ch0-ch3 and com pins can have any value between gnd C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and underrange output codes. ch0 to ch3 (pin 8-pin 11): analog inputs. may be pro- grammed for single-ended or differential mode. v cc (pin 12): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + , ref C (pin 13, pin 14): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 0.1v. the differential voltage (v ref = ref + C ref C ) sets the full-scale range for all input channels. when performing an on-chip temperature measurement, the minimum value of ref = 2v. exposed pad (pin 15): ground. this pin is ground and must be soldered to the pcb ground plane. for prototyping purposes, this pin may remain floating.
ltc2493 12 2493fd f unc t ional b lock diagra m autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator i 2 c interface gnd v cc ch0 ch1 ch2 ch3 com mux in + in ? ca0 scl ref + ref ? ca1 sda f o (int/ext) 2493 bd + ? 1.7k temp sensor
ltc2493 13 2493fd converter operation converter operation cycle the ltc2493 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, i 2 c interface. its operation is made up of four states (see figure 1). the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/ output cycle. initially, at power-up, the ltc2493 performs a conversion. once the conversion is complete, the device enters the sleep state. while in the sleep state, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long it is not addressed for a read/ write operation. the conversion result is held indefinitely in a static shift register while the part is in the sleep state. the device will not acknowledge an external request dur - ing the conversion state. after a conversion is finished, the device is ready to accept a read/write request. once the ltc2493 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conver - sion result. the data output is 32 bits long and contains a 24-bit plus sign conversion result. data is updated on the falling edges of scl allowing the user to reliably latch data on the rising edge of scl. a new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. the conversion automatically begins at the conclusion of a complete read cycle (all 32 bits read out of the device). ease of use the ltc2493 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straightforward. each conversion, immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. the ltc2493 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user and has no effect on the operation cycle previ- a pplica t ions i n f or m a t ion figure 1. state transition table conversion sleep 2493 f01 yes no acknowledge yes no stop or read 32 bits data output/input power-on reset default configuration: in + = ch0, in ? = ch1 50hz/60hz rejection 1x output ously described. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel and temperature drift. easy drive input current cancellation the ltc2493 combines a high precision, delta-sigma adc with an automatic, differential, input current cancellation front end. a proprietary front end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sen- sors to directly interface to the ltc2493 without external amplifiers. the remaining common mode input current is eliminated by either balancing the differential input im - pedances or setting the common mode input equal to the common mode reference (see the automatic differential input current cancellation section). this unique architec - ture does not require on-chip buffers, thereby enabling
ltc2493 14 2493fd signals to swing beyond ground and v cc . moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full-scale + offset + linearity + drift) is maintained even with external rc networks. power-up sequence the ltc2493 automatically enters an internal reset state when the power supply voltage, v cc , drops below ap- proximately 2.0v. this feature guarantees the integrity of the conversion result and input channel selection. when v cc rises above this threshold, the converter creates an internal power-on reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channel in + = ch0, in C = ch1 with simultaneous 50hz/60hz rejection and 1x output rate. the first conversion following a por cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7v to 5.5v) before the end of the por interval. a new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this first data input/output cycle. reference voltage range this converter accepts a truly differential external refer - ence voltage. the absolute/common mode voltage range for the ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref C ). the ltc2493 differential reference input range is 0.1v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. the converter out- put noise is determined by the thermal noise of the front end circuits and, as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effec - tive resolution. on the other hand, a decreased reference will improve the converters overall inl performance. input voltage range the analog inputs are truly differential with an absolute, common mode range for the ch0-ch3 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2493 converts the bipolar dif - ferential input signal v in = in + C in C (where in + and in C are the selected input channels), from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + - ref C . outside this range, the converter indicates the overrange or the under - range condition using distinct output codes (see table 1). in order to limit any fault current, resistors of up to 5k may be added in series with the input. the effect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference cur - rent sections. in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. i 2 c interface the ltc2493 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. the connected devices can only pull the data line (sda) low and can never drive it high. sda is required to be exter - nally connected to the supply through a pull-up resistor. when the data line is not being driven, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. the v cc power should not be removed from the device when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when perform - ing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals a pplica t ions i n f or m a t ion
ltc2493 15 2493fd to permit that transfer. devices addressed by the master are considered a slave. the ltc2493 can only be addressed as a slave. once addressed, it can receive configuration bits (channel selection, rejection mode, speed mode) or transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2493 and the serial data line sda is bidirectional. the device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. figure 2 shows the definition of the i 2 c timing. the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is finished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nack) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. data format after a start condition, the master sends a 7-bit address followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit ad- dress matches the hard wired ltc2493s address (one of 9 pin-selectable addresses) the device is selected. when the device is addressed during the conversion state, it will not acknowledge r/w requests and will issue a nack by leaving the sda line high. if the conversion is complete, the ltc2493 issues an ack by pulling the sda line low. the ltc2493 has two registers. the output register (32 bits long) contains the last conversion result. the input register (16 bits long) sets the input channel, selects the temperature sensor, rejection mode, and speed mode. sda scl s sr p s t hd(sda) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2493 f02 figure 2. definition of timing for fast/standard mode devices on the i 2 c bus a pplica t ions i n f or m a t ion
ltc2493 16 2493fd data output format the output register contains the last conversion result. after each conversion is completed, the device automati- cally enters the sleep state where the supply current is reduced to 1a. when the ltc2493 is addressed for a read operation, it acknowledges (by pulling sda low) and acts as a transmitter. the master/receiver can read up to four bytes from the ltc2493. after a complete read operation (4 bytes), a new conversion is initiated. the device will nack subsequent read operations while a conversion is being performed. the data output stream is 32 bits long and is shifted out on the falling edges of scl (see figure 3a). the first bit is the conversion result sign bit (sig) (see tables 1 and 2). this bit is high if v in 0 and low if v in < 0 (where v in corresponds to the selected input signal in + C in C ). the second bit is the most significant bit (msb) of the result. the first two bits (sig and msb) can be used to indicate over and under range conditions (see table 2). if both bits are high, the differential input voltage is equal to or above +fs. if both bits are set low, the input voltage is below Cfs. table 1. output data format differential input voltage v in * bit 31 sig bit 30 msb bit 29 bit 28 bit 27 bit 6 lsb bits 5-0 sub lsbs v in * fs** 1 1 0 0 0 0 00000 fs** C 1 lsb 1 0 1 1 1 1 xxxxx 0.5 ? fs** 1 0 1 0 0 0 xxxxx 0.5 ? fs** C 1 lsb 1 0 0 1 1 1 xxxxx 0 1/0 ? 0 0 0 0 0 xxxxx C1 lsb 0 1 1 1 1 1 xxxxx C0.5 ? fs** 0 1 1 0 0 0 xxxxx C0.5 ? fs** C 1 lsb 0 1 0 1 1 1 xxxxx Cfs** 0 1 0 0 0 0 xxxxx v in * < Cfs** 0 0 1 1 1 1 11111 *the differential input voltage v in = in + C in C . **the full-scale voltage fs = 0.5 ? v ref . sub lsbs are below the 24-bit level. they may be included in averaging, or discarded without loss of resolution. ? the sign bit changes state during the 0 output code when the device is operating in the 2x speed mode. the function of these bits is summarized in table 2. the 24 bits following the msb bit are the conversion result in binary twos, complement format. the remaining six bits are sub lsbs below the 24-bit level. as long as the voltage on the selected input channels (in + and in C ) remains between C0.3v and v cc + 0.3v (absolute maximum operating range) a conversion result is gener - ated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to +fs. for differential input volt - ages below Cfs, the conversion result is clamped to the value Cfs C 1 lsb. table 2. ltc2493 status bits input range bit 31 sig bit 30 msb v in fs 1 1 0v v in < fs 1/ 0 0 Cfs v in < 0v 0 1 v in < Cfs 0 0 a pplica t ions i n f or m a t ion
ltc2493 17 2493fd input data format the serial input word to the ltc2493 is 13 bits long and is written into the device input register in two 8-bit words. the first word (sgl, odd, a2, a1, a0) is used to select the input channel. the second word of data (im, fa, fb, spd) is used to select the frequency rejection, speed mode (1, 2), and temperature measurement. after power-up, the device initiates an internal reset cycle which sets the input channel to ch0-ch1 (in + = ch0, in C = ch1), the frequency rejection to simultaneous 50hz/60hz, and 1 output rate (auto-calibration enabled). the first conversion automatically begins at power-up using this default configuration. once the conversion is complete, up to two words may be written into the device. the first three bits of the first input word consist of two preamble bits and one enable bit. valid settings for these three bits are 000, 100, and 101. other combinations should be avoided. if the first three bits are 000 or 100, the following data is ignored (dont care) and the previously selected input channel remains valid for the next conversion. if the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see table 3). figure 3a. timing diagram for reading from the ltc2493 a pplica t ions i n f or m a t ion sleep data output ack by ltc2493 ack by master sub lsbs start by master nack by master lsb r msb sig d31 7 ? ? 8 9 1 2 9 1 2 3 4 5 6 7 8 9 1 7-bit address 2493 f03a scl sda sleep data input ack by ltc2493 ack by ltc2493 ack by ltc2493 (optional 2nd byte) start by master sgl odd w 0 1 scl sda en a2 a1 a0 7 ? 8 9 1 2 9 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 1 7-bit address 2493 f03b im fa en2 fb spd figure 3b. timing diagram for writing to the ltc2493 table 3. channel selection mux address channel selection sgl odd/ sign a2 a1 a0 0 1 2 3 com *0 0 0 0 0 in + in C 0 0 0 0 1 in + in C 0 1 0 0 0 in C in + 0 1 0 0 1 in C in + 1 0 0 0 0 in + in C 1 0 0 0 1 in + in C 1 1 0 0 0 in + in C 1 1 0 0 1 in + in C *default at power-up
ltc2493 18 2493fd the first input bit (sgl) following the 101 sequence de - te rmines if the input selection is differential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent chan- nels can be selected to form a differential input. for sgl = 1, one of four channels is selected as the positive input. the negative input is com for all single-ended operations. the remaining four bits (odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity (for a differential input). once the first word is written into the device, a second word may be input in order to select a configuration mode. the first bit of the second word is the enable bit for the conversion configuration (en2). if this bit is set to 0, then the next conversion is performed using the previously selected converter configuration. the second set of configuration data can be loaded into the device by setting en2 = 1 (see table 4). the first bit (im) is used to select the internal temperature sensor. if im = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. the next two bits (fa and fb) are used to set the rejection frequency. the final bit (spd) is used to select either the 1 output rate if spd = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the final conversion result) or the 2 output rate if spd = 1 (offset calibration disabled, multiplexing output rates up to 15hz with no latency). when im = 1 (temperature measurement) spd will be ignored and the device will operate in 1 mode. the configuration remains valid until a new input word with en = 1 (the first three bits are 101 for the first word) and en2 = 1 (for the second write byte) is shifted into the device. rejection mode (fa, fb) the ltc2493 includes a high accuracy on-chip oscillator with no required external components. coupled with an integrated fourth order digital lowpass filter, the ltc2493 rejects line frequency noise. in the default mode, the ltc2493 simultaneously rejects 50hz and 60hz by at least 87db. if more rejection is required, the ltc2493 can be configured to reject 50hz or 60hz to better than 110db. table 4. converter configuration 1 0 en sgl odd a2 a1 a0 en2 im fa fb spd converter configuration 1 0 0 x x x x x x x x x x keep previous 1 0 1 x x x x x 0 x x x x keep previous 0 0 1 x x x x x x x x x x keep previous 1 0 1 x x x x x 1 0 0 0 0 external input (see table 3) 50hz/60hz rejection, 1 1 0 1 x x x x x 1 0 0 1 0 external input (see table 3) 50hz rejection, 1 1 0 1 x x x x x 1 0 1 0 0 external input (see table 3) 60hz rejection, 1 1 0 1 x x x x x 1 0 0 0 1 external input (see table 3) 50hz/60hz rejection, 2 1 0 1 x x x x x 1 0 0 1 1 external input (see table 3) 50hz rejection, 2 1 0 1 x x x x x 1 0 1 0 1 external input (see table 3) 60hz rejection, 2 1 0 1 x x x x x 1 1 0 0 x measure temperature 50hz/60hz rejection, 1 1 0 1 x x x x x 1 1 0 1 x measure temperature 50hz rejection, 1 1 0 1 x x x x x 1 1 1 0 x measure temperature 60hz rejection, 1 1 0 1 x x x x x 1 x 1 1 x reserved, do not use a pplica t ions i n f or m a t ion
ltc2493 19 2493fd speed mode (spd) every conversion cycle, two conversions are combined to remove the offset (default mode). this result is free from offset and drift. in applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. while operating in the 2 mode (spd = 1), the linearity and full-scale errors are unchanged from the 2 mode performance. in both the 2 and 2 mode there is no latency. this enables input steps or multiplexer changes to settle in a single conversion cycle, easing system over - head and increasing the effective conversion rate. during temperature measurements, the 1 mode is always used independent of the value of spd. temperature sensor the ltc2493 includes an integrated temperature sen - sor. the temperature sensor is selected by setting im = 1. the adc internally connects to the temperature sensor and performs a conversion. the digital output is proportional to the absolute tem- perature of the device. this feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. the internal temperature sensor output is 28mv at 27c (300k), with a slope of 93.5v/c independent of v ref (see figures 4 and 5). slope calibration is not required if the reference voltage (v ref ) is known. a 5v reference has a slope of 314 lsbs 24 /c. the temperature is calculated from the output code (where dataout 24 is the decimal representation of the 24-bit result) for a 5v reference using the following formula: t k = dataout 24 314 in kelvin if a different value of v ref is used, the temperature output is: t k = dataout 24 ? v ref 1570 in kelvin if the value of v ref is not known, the slope is determined by measuring the temperature sensor at a known tempera- ture t n (in k) and using the following formula: slope = dataout 24 t n this value of slope can be used to calculate further tem- perature readings using: t k = dataout 24 slope all kelvin temperature readings can be converted to t c (c) using the fundamental equation: t c = t k C 273 temperature (k) 0 dataout 24 60000 80000 100000 120000 140000 400 2493 f04 40000 0 300 200 100 20000 v cc = 5v v ref = 5v slope = 314 lsb 24 /k temperature (c) ?55 ?30 ?5 absolute error (c) 5 4 3 2 1 ?4 ?3 ?2 ?1 0 12095704520 2493 f05 ?5 figure 4. internal ptat digital output vs temperature figure 5. absolute temperature error a pplica t ions i n f or m a t ion
ltc2493 20 2493fd s ack d at a sr dat a transferring p 7-bit address r/w 2493 f05 conversion conversion sleep data input/output figure 6. conversion sequence initiating a new conversion when the ltc2493 finishes a conversion, it automatically enters the sleep state. once in the sleep state, the device is ready for a read operation. after the device acknowledges a read request, the device exits the sleep state and enters the data output state. the data output state concludes and the ltc2493 starts a new conversion once a stop condition is issued by the master or all 32 bits of data are read out of the device. during the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. this stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ack/nack cycle). ltc2493 address the ltc2493 has two address pins (ca0, ca1). each may be tied high, low, or left floating enabling one of nine possible addresses (see table 5). in addition to the configurable addresses listed in table 5, the ltc2493 also contains a global address (1110111) which may be used for synchronizing multiple l tc2493s or other ltc24xx delta-sigma i 2 c devices (see synchronizing multiple ltc2493s with a global address call section). operation sequence the ltc2493 acts as a transmitter or receiver, as shown in figure 6. the device may be programmed to perform several functions. these include input channel selection, measure the internal temperature, selecting the line fre- quency rejection (50hz, 60hz, or simultaneous 50hz and 60hz) and a 2 speed mode. continuous read in applications where the input channel/configuration does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see figure 7). the configuration/input channel remains unchanged from the last value written into the device. if the device has not been written to since power-up, the configuration is set to the default value. at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2493 generates a nack signal indicating the conversion cycle is in progress. a pplica t ions i n f or m a t ion table 5. address assignment ca1 ca0 address low low 0010100 low high 0010110 low float 0010101 high low 0100110 high high 0110100 high float 0100111 float low 0010111 float high 0100101 float float 0100100
ltc2493 21 2493fd 7-bit address 7-bit address s s r r ack ack read read p p 2493 f07 conversion conversion conversion sleep data output dat a input sleep 7-bit address 7-bit address s r w ack ack write sr p read 2493 f08 conversion conversion address sleep data output dat a input 7-bit address s w ack write (optional) p 2493 f09 conversion conversion sleep d at a input figure 7. consecutive reading with the same input/configuration figure 8. write, read, start conversion figure 9. start a new conversion without reading old conversion result a pplica t ions i n f or m a t ion continuous read/write once the conversion cycle is concluded, the ltc2493 can be written to and then read from using the repeated start (sr) command. figure 8 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. the following conversion begins after all 32 bits are read out of the device or after a stop com - mand. the following conversion will be performed using the newly programmed data. in cases where the same speed (1/2 mode) and rejection frequency (50hz, 60hz, 50hz and 60hz) is used but the channel is changed, a stop or r epeated start may be issued after the first byte (channel selection data) is written into the device. discarding a conversion result and initiating a new conversion with optional write at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop command will start a new conversion. if a new input channel or conversion configuration is required, this data can be written into the device and a stop command will initiate the next conversion (see figure 9).
ltc2493 22 2493fd figure 11. equivalent analog input circuit ii ni in vv r avg avg in cm re fc m eq + () = () = ? ? ? () () . 05 i ir ef vv v r avg re fr ef cm in cm + () + () 15 05 .? .? () () e eq in re fe q re f re fc m v vr wh er e vr ef re f v ? ? : ( 2 =? +? )) ? , = ? ? ? ? ? ? ? ? =? +? +? + re fr ef vi ni nw here in an in 2 d di na re th es elected in pu tc hann els v in in cm ? + = () ?? . in rm in terna lo sci llator eq ? ? ? ? ? ? ? ? ? = 2 27 16 0 0h zm ode r 2.98 mi nte rna lo sci llator 50h z/ 60 eq = h hz m ode r 0.833 10 /f exte rna lo sci l eq 12 eo sc =? () llator in + in ? 10k internal switch network 10k c eq 12f 10k i in ? ref + i ref + i in + i ref ? 2493 f11a switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator ref ? 10k 100 input multiplexer 100 synchronizing multiple ltc2493s with a global address call in applications where several ltc2493s (or other i 2 c delta-sigma adcs from linear technology corporation) are used on the same i 2 c bus, all converters can be syn- chronized through the use of a global address call. prior to issuing the global address call, all converters must have completed a conversion cycle. the master then is- sues a start, followed by the global address 1110111, and a write request. all converters will be selected and acknowledge the request. the master then sends a write byte (optional) followed by the stop command. this will update the channel selection (optional) converter configuration (optional) and simultaneously initiate a start of conversion for all delta-sigma adcs on the bus (see global address scl sda ltc2493 ltc2493 ltc2493 ? s w ack write (optional) p 2493 f10 all ltc2493s in sleep conversion of all ltc2493s data input figure 10. synchronize multiple ltc2493s with a global address call figure 10). in order to synchronize multiple converters without changing the channel or configuration, a stop may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nack a global read request. driving the input and reference the input and reference pins of the ltc2493 are connected directly to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simplified equivalent circuit is shown in figure 11. a pplica t ions i n f or m a t ion
ltc2493 23 2493fd when using the ltc2493s internal oscillator, the input capacitor array is switched at 123khz. the effect of the charge transfer depends on the circuitry driving the input/ reference pins. if the total external rc time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. typically, the reference inputs are driven from a low im - pedance source. in this case, complete settling occurs even with large external bypass capacitors. the inputs (ch0-ch3, com), on the other hand, are typically driven from larger source resistances. source resistances up to 10k may interface directly to the ltc2493 and settle completely; however, the addition of external capacitors at the input terminals in order to filter unwanted noise (anti-aliasing) results in incomplete settling. automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2493 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. this allows direct digitization of high impedance sensors without the need for buffers. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v in(cm) ) and the common mode reference voltage (v ref(cm) ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and com- mon mode input current are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5v and an input common mode of 1.5v, the common mode input current is approximately 0.74a (in simultaneous 50hz/60hz rejection mode). this common mode input current does not degrade the accuracy if the source impedances tied to in + and in C are matched. mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full-scale reading. a 1% mismatch in a 1k source resistance leads to a 74v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2493, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the dif- ference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. based on the stability of the internal sampling capacitors and the ac- curacy of the internal oscillator, a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and a 10v maximum offset voltage. a pplica t ions i n f or m a t ion
ltc2493 24 2493fd r source () 0 +fs error (ppm) 50 70 90 10k 2493 f12 30 10 40 60 80 20 0 ?10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source () 0 ?fs error (ppm) ?30 ?10 10 10k 2493 f13 ?50 ?70 ?40 ?20 0 ?60 ?80 ?90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source () 0 +fs error (ppm) 300 400 500 800 2493 f14 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c ref = 1 f, 10f c ref = 0.1 f c ref = 0.01 f r source () 0 ?fs error (ppm) ?200 ?100 0 800 2493 f15 ?300 ? 400 ?500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c ref = 1 f, 10f c ref = 0.1 f c ref = 0.01 f reference current similar to the analog inputs, the ltc2493 samples the differential reference pins (ref + and ref C ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete set- tling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capacitance (c ref < 1nf), the voltage on the sampling capacitor settles for reference impedances of many k ( if c ref = 100pf up to 10k will not degrade the performance (see figures 12 and 13) ) . in cases where large bypass capacitors are required on the reference inputs (c ref > .01f), full-scale and linear - ity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5ppm ( while operat- ing in simultaneous 50hz/60hz mode (see figures 14 and 15) ) . if the input common mode voltage is equal to figure 12. +fs error vs r source at v ref (small c ref ) figure 13. Cfs error vs r source at v ref (small c ref ) figure 14. +fs error vs r source at v ref (large c ref ) figure 15. Cfs error vs r source at v ref (large c ref ) a pplica t ions i n f or m a t ion
ltc2493 25 2493fd the sinc 4 digital filter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ) (see figures 17 and 18). the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . figure 16. inl vs differential input voltage and reference source resistance for c ref > 1f figure 18. input normal mode rejection, internal oscillator and 60hz rejection mode figure 17. input normal mode rejection, internal oscillator and 50hz rejection mode the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 of reference resistance results (see figure 16). in applications where the input and reference common mode voltages are different, the errors increase. a 1v difference in between common mode input and common mode reference results in a 6.7ppm inl error for every 100 of reference resistance. in addition to the reference sampling charge, the reference esd protection diodes have a temperature dependent leak- age current. this leakage current, nominally 1na (10na max) results in a small gain error. a 100 reference resistance will create a 0.5v full-scale error. normal mode rejection and anti-aliasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital filtering. combined with a large oversample ratio, the ltc2493 significantly simplifies anti-aliasing filter requirements. additionally, the input current cancellation feature allows external lowpass filtering without degrading the dc performance of the device. a pplica t ions i n f or m a t ion v in /v ref ? 0.5 inl (ppm of v ref ) 2 6 10 0.3 2493 f16 ?2 ? 6 0 4 8 ?4 ? 8 ?10 ? 0.3 ? 0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 differential input signal frequency (hz) 0 f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2493 f17 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 differential input signal frequency (hz) 0 f s input normal mode rejection (db) 2493 f18 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s
ltc2493 26 2493fd figure 20. input normal mode rejection at f s = 256 ? f n figure 19. input normal mode rejection at dc when using the internal oscillator, the ltc2493 is designed to reject line frequencies. as shown in figure 19, rejec- tion nulls occur at multiples of frequency f n , where f n is determined by the input control bits fa and fb (f n = 50hz or 60hz or 55hz for simultaneous rejection). multiples of the modulator sampling rate (f s = f n ? 256) only reject noise to 15db (see figure 20); if noise sources are present at these frequencies anti-aliasing will reduce their effects. the user can expect to achieve this level of performance using the internal oscillator, as shown in figures 21, 22, and 23. measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. a pplica t ions i n f or m a t ion input signal frequency (hz) input normal mode rejection (db) 2493 f19 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2493 f20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 f n = f eosc/5120 traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2493 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. in many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. figures 24 and 25 show measurement results for the rejection of a 7.5v peak-to-peak noise source (150% of full-scale) applied to the ltc2493. these curves show that the rejection perfor - mance is maintained even in extremely noisy environments.
ltc2493 27 2493fd figure 21. input normal mode rejection vs input frequency with input perturbation of 100% (60hz notch) figure 22. input normal mode rejection vs input frequency with input perturbation of 100% (50hz notch) figure 25. measure input normal mode rejection vs input frequency with input perturbation of 150% (50hz notch) figure 23. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) figure 24. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch) a pplica t ions i n f or m a t ion input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2493 f21 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2493 f22 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2493 f23 0 ?20 ? 40 ? 60 ? 80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2493 f24 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2493 f25 0 ?20 ? 40 ? 60 ? 80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
ltc2493 28 2493fd using the 2 speed mode of the ltc2493 alters the rejec- tion characteristics around dc and multiples of f s . the device bypasses the offset calibration in order to increase the output rate. the resulting rejection plots are shown in figures 26 and 27. 1 type frequency rejection can be achieved using the 2 mode by performing a running aver - age of the previous two conversion results (see figure 28). output data rate when using its internal oscillator, the ltc2493 produces up to 15 samples per second (sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. when operating with an external conversion clock (f o connected to an external oscillator), the ltc2493 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used. an increase in f eosc over the nominal 307.2khz will trans- late into a proportional increase in the maximum output data rate (up to a maximum of 100sps). the increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejec- tion. when using the integrated temperature sensor, the internal oscillator should be used or an external oscillator f eosc = 307.2khz maximum. a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in C pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1mhz (a more than 3 increase in output rate) the effectiveness of internal auto-calibration circuits begins to degrade. this results in larger offset errors, full-scale errors, and decreased resolution, as seen in figures 29-36. figure 26. input normal mode rejection 2 speed mode figure 27. input normal mode rejection 2 speed mode a pplica t ions i n f or m a t ion input signal frequency (f n ) input normal rejection (db) 2493 f26 0 ?20 ? 40 ?60 ?80 ?100 ?120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (f n ) input normal rejection (db) 2493 f27 0 ?20 ?40 ?60 ?80 ?100 ?120 250248 252 254 256 258 260 262 264
ltc2493 29 2493fd figure 28. input normal mode rejection 2 speed mode with and without running averaging figure 29. offset error vs output data rate and temperature figure 30. +fs error vs output data rate and temperature figure 31.Cfs error vs output data rate and temperature figure 32. resolution (noise rms 1 lsb) vs output data rate and temperature figure 33. resolution (inl max 1 lsb) vs output data rate and temperature figure 35. resolution (noise rms 1 lsb) vs output data rate and temperature figure 36. resolution (inl max 1 lsb) vs output data rate and temperature figure 34. offset error vs output data rate and temperature a pplica t ions i n f or m a t ion differential input signal frequency (hz) 48 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 54 58 2493 f28 50 52 56 60 62 normal mode rejection (db) no average with running average output data rate (readings/sec) ?10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2493 f29 100 100 30 50 70 90 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2493 f30 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 ?3500 ? fs error (ppm of v ref ) ?3000 ?2000 ?1500 ?1000 0 10 50 70 2493 f31 ?2500 ? 500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2493 f32 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2493 f33 14 20 40 90 100 20 30 60 80 t a = 85c t a = 25c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) output data rate (readings/sec) 0 ?10 offset error (ppm of v ref ) ?5 5 10 20 10 50 70 2493 f34 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2493 f35 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2493 f36 14 20 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref ? = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max )
ltc2493 30 2493fd p ackage descrip t ion easy drive adcs simplify measurement of high impedance sensors delta-sigma adcs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. nevertheless, input sampling currents can overwhelm high source impedances or low bandwidth, micropower signal conditioning circuits. the ltc2493 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. a common application for a delta-sigma adc is thermistor measurement. figure 37 shows two examples of thermis- tor digitization benefiting from the easy drive technology. the first circuit (applied to input channels ch0 and ch1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. if reference resistors r1 and r4 are exactly equal, the input current is zero and no errors result. if these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6 due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. no amplifier is required, making this an ideal solution in micropower applications. easy drive also enables very low power, low bandwidth amplifiers to drive the input to the ltc2493. as shown in figure 7, ch2 is driven by the lt1494. the lt1494 has excellent dc specs for an amplifier with 1.5a supply current (the maximum offset voltage is 150v and the open-loop gain is 100,000). its 2khz bandwidth makes it unsuitable for driving conventional delta-sigma adcs. adding a 1k, 0.1f filter solves this problem by providing a charge reservoir that supplies the ltc2493 instantaneous current, while the 1k resistor isolates the capacitive load from the lt1494. conventional delta-sigma adcs input sampling current lead to dc errors as a result of incomplete settling in the external rc network. the easy drive technology cancels the differential input current. by balancing the negative input (ch3) with a 1k, 0.1f network errors due to the common mode input current are cancelled. de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) a pplica t ions i n f or m a t ion 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 3.30 0.10 1.70 0.05 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 0.50 bsc
ltc2493 31 2493fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 11/09 update tables 1 and 2 16 d 07/10 revised typical application drawing 1 added f o pin to parameters of v iha in i 2 c inputs and digital outputs section 4 added information to i 2 c interface section 14 (revision history begins at rev c)
ltc2493 32 2493fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2006 lt 0710 rev d ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error , 200a ltc2410 24-bit, no latency ? adc with differential inputs 0.8v rms noise, 2ppm inl ltc2440 24-bit, high speed, low noise ? adc 3.5khz output rate, 200nv noise, 24.6 enobs ltc2442 24-bit, high speed, 2-/4-channel ? adc with integrated amplifier 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2449 24-bit, high speed, 8-/16-channel ? adc 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2480/l tc2482/ ltc2484 16-bit/24-bit ? adcs with easy drive inputs, 600nv noise, programmable gain, and temperature sensor pin compatible 16-bit and 24-bit v ersions ltc2481/ltc2483/ ltc2485 16-bit/24-bit ? adcs with easy drive inputs, 600nv noise, i 2 c interface, programmable gain, and temperature sensor pin compatible 16-bit and 24-bit versions ltc2486/ltc2488/ ltc2492 16-bit/24-bit 2-/4-channel ? adc with easy drive inputs, spi interface, programmable gain, and t emperature sensor pin-compatible 16-bit and 24-bit versions ltc2487 16-bit 2-/4-channel ? adc with easy drive inputs and i 2 c interface, temperature sensor pin-compatible with ltc2493/ltc2489 ltc2489 16-bit 2-/4-channel ? adc with easy drive inputs pin-compatible with ltc2487/l tc2493 ltc2495/ltc2497/ ltc2499 16-bit/24-bit 8-/16-channel ? adc with easy drive inputs and i 2 c interface, programmable gain, and temperature sensor pin-compatible 16-bit and 24-bit versions ltc2496/ltc2498 16-bit 8-/16-channel ? adc with easy drive inputs and spi inter face pin-compatible with ltc2498/ltc2449 figure 37. easy drive adcs simplify measurement of high impedance sensors v cc f o scl sda gnd = external oscillator = internal oscillator ltc2493 2-wire i 2 c interface 9-pin selectable addresses 2493 f37 ca0 12 1 ref + 13 ref ? 14 ch0 8 ch1 9 ch2 10 ch3 11 com 7 4 2 6 3 5 5v 0.1f 10f ca1 5v i in + = 0 i in ? = 0 r1 51.1k r4 51.1k c4 0.1 f c3 0.1 f r3 10k to 100k ? + 102k 5v 5v lt1494 0.1 f 0.1 f 0.1 f 1k 1k 10k to 100k 1.7k

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